R&D Engineering, Sr Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the trenches of physical design, where the difference between a chip that tapes out clean and one that needs a respin often comes down to a timing path you caught at 2 AM or a power grid issue you debugged across three tool domains. You know that place and route is not just about closing timing, it is about understanding the tradeoffs between power, performance, and area well enough to make the right call when all three are pulling in different directions.

You are comfortable opening Fusion Compiler on Monday to close a complex hierarchical design and then jumping into PrimeTime or StarRC on Tuesday to figure out why a corner case is failing signoff. Real tape-out experience has taught you that the methodology matters as much as the result, and you care about building flows that do not just work once but scale across projects and teams.

Working with foundries does not intimidate you. You have debugged enough DRC violations and worked through enough DTCO discussions to know how to translate between what a process team needs and what an implementation flow can actually deliver. You ask the right questions, push back when something does not make sense, and find a path forward without waiting for perfect clarity.

At Synopsys, you will work directly with foundry partners and advanced node enablement teams on designs that define what is possible at the next process node.

What You'll Be Doing

• Develop and optimize foundry implementation and 3DIC solutions using Synopsys Fusion Compiler, aligned with reference methodology and advanced node requirements
• Provide direct engineering support to foundry partners and end customers on DTCO, PPA optimization, and test chip bring-up for cutting-edge process nodes
• Debug complex place and route, timing, power, and physical verification issues across multi-corner, multi-mode designs using tools like PrimeTime, StarRC, IC Validator, and RedHawk
• Drive foundry test chip projects from RTL to GDS, coordinating with Synopsys advanced node enablement teams and foundry process groups
• Work with field account teams and internal jumpstart teams to support mutual customer engagements and accelerate adoption of Synopsys physical design solutions
• Collaborate with cross-functional engineering teams across geographies to resolve real project issues, improve implementation flows, and close PPA gaps
• Explore and integrate productivity improvements using modern engineering tools and AI-assisted solutions like Cursor to accelerate design and debug cycles

The Impact You Will Have

• Enable successful tape-outs at advanced nodes by delivering optimized physical design solutions that meet aggressive PPA targets
• Accelerate foundry partner readiness and customer adoption of next-generation process technologies through hands-on implementation support and flow development
• Improve design quality and reduce iteration cycles by identifying and resolving complex timing, power, and signoff issues before they reach customers
• Influence foundry roadmap decisions and design rule development by providing real-world feedback from test chip implementation and customer engagements
• Build reusable methodologies and automation that scale across multiple projects, reducing bring-up time for future advanced node designs
• Strengthen customer relationships and drive tool adoption by solving critical design challenges that directly impact their product schedules
• Contribute to the continuous improvement of Synopsys physical design tools and flows based on frontline experience with the hardest implementation problems

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering with 2+ years of hands-on experience in physical design implementation
• Proficiency in place and route methodology, hierarchical design, and timing signoff using Synopsys Fusion Compiler or equivalent P&R tools
• Hands-on experience with physical design signoff tools such as PrimeTime for timing, StarRC for extraction, IC Validator for DRC/LVS, or RedHawk for power analysis
• Demonstrated ability to debug complex implementation issues across multiple domains including timing closure, power integrity, and physical verification
• Experience working on high-performance or low-power designs with a track record of contributing to PPA improvements and flow optimization
• Real tape-out experience on SoC, CPU, or GPU projects is a strong plus
• Exposure to AI-assisted engineering tools like Cursor or similar automation frameworks is a plus

Who You Are

• You can take a failing timing path, trace it back through multiple hierarchy levels, and figure out whether the issue is floorplan, placement, routing, or something upstream in synthesis
• You communicate technical tradeoffs clearly enough that a foundry process engineer and a customer design lead can both understand the same issue and align on next steps
• You do not wait for someone to hand you a perfect flow, you look at what is breaking, figure out what needs to change, and build the automation or methodology to fix it
• You are comfortable working across time zones and cultures, coordinating with teams in different geographies without losing momentum or clarity
• You take ownership of the designs and flows you touch, but you also know when to pull in the right people and escalate issues that need broader attention
• You stay curious about new approaches, whether that is a different floorplanning strategy, a new signoff corner, or an AI tool that might cut debug time in half

The Team You'll Be Part Of

You will be part of a dynamic and innovative team focused on developing cutting-edge foundry P&R implementation/3DIC/AI solutions with supporting foundry test chip projects. Our team collaborates closely with foundry, internal teams, and end customers to drive technological advancements and optimize implementation/3DIC flows. We value creativity, teamwork, and a commitment to excellence in all our projects.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

#TPG