Nuvacore is building a ground-up CPU silicon for next-generation compute workloads. As our CPU Performance Modeling Lead, you will own the performance modeling infrastructure and methodology that drives every architectural decision we make — from early pathfinding through tape-out and post-silicon correlation.
THE ROLE
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Design, develop and own Nuvacore’s cycle-accurate CPU performance simulator — its architecture, fidelity, and long-term roadmap — as the authoritative reference model for the design team.
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Lead microarchitectural exploration across all major CPU domains: frontend (fetch, decode, branch prediction), out-of-order engine (rename, dispatch, execution), and memory subsystem (caches, prefetchers, TLBs, coherence).
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Drive model-to-RTL correlation through all execution phases; own debug and resolution of performance miscorrelation between the performance model, RTL simulation, and post-silicon results.
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Collaborate closely with design, verification, compiler, and system software teams to align architecture decisions with implementation constraints and software stack realities.
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Mentor engineers across the performance team; provide technical leadership on modeling methodology, simulation infrastructure, and analysis tooling.
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Contribute to IP development through patents and, where applicable, external publication
REQUIREMENTS — MUST HAVE
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MS in Computer Architecture, Computer Engineering, or related field (PhD preferred).
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20+ years (Lead) or 8+ years (ICs) in CPU microarchitecture and/or performance engineering.
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20+ years (Lead) or 8+ years (ICs) of hands-on experience with cycle-accurate C++ CPU performance simulators (e.g. gem5 or equivalent in-house tools).
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Deep expertise in at least one of: branch prediction, fetch/decode, rename/dispatch, OOO execution, memory subsystem, or prefetchers.
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Strong C++ and Python / Perl skills; ability to write and analyze assembly for microarchitectural test cases.
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Proven track record driving performance from pathfinding through silicon (RTL correlation and/or post-Si debug).
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Experience in RISC-V or ARM64 or x86 ISA.
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Strong track record in identifying ideas to improve power/performance/area (PPA) of CPUs.
- Experience developing trace-based and execution-driven CPU performance simulators.
REQUIREMENTS — NICE TO HAVE
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Experience with compiler optimizations and hardware/software co-design.
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Published work or filed patents in CPU performance or microarchitecture.
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Prior principal-level role at a CPU design organization.